Recently, along with progress in high integration of a semiconductor element and a reduction in chip size, finer wiring and multilayer wiring are acceleratingly promoted. In a logic device having such a multilayer wiring, wiring delay is becoming one of factors governing device signal delay. The device signal delay is proportional to the product of wiring resistance value and wiring capacity, and hence, to improve wiring delay, more specifically to improve operating speed of the device, a reduction mainly in a wiring resistance value is important.
To reduce the wiring resistance, formation of a Cu wiring instead of a conventional Al wiring is studied. However, under the circumstances of a material characteristic of copper and the reduction in chip size described above, a technical limit begins to occur in a method of forming the Cu wiring by directly etching the Cu film. Therefore, a method called damascene process, in which wiring is formed by a hole pattern or trench pattern being formed in an interlayer insulating film and a Cu wiring material being embedded therein, is rapidly being developed.
Also, recently, to increase operational speed of a device, a reduction in electric capacity (wiring capacity) in the same layer and between different layers is beginning to be required. Under the circumstances, adopting a low dielectric constant insulating film as the interlayer insulating film is suggested. However, the low dielectric constant insulating film is quite different from a conventional material based on a silicon oxide film such as having a siloxane bond, in physicality values such as Young's modulus, hardness, and thermal expansion, and the following problems in manufacturing processes are caused thereby.
In general, for the low dielectric constant, a change in structure inside materials such as of an atom or a molecule is necessary. If a distance between atoms or a distance between molecules is increased, the dielectric constant is lowered, but at the same time, cohesive strength is decreased since the distance between atoms or the distance between molecules is increased, with the material becoming susceptible in terms of heat or mechanical characteristic, tolerance to chemicals, and the like.
In a pad region of an LSI formed by fine processing, it is necessary to eventually form an electrode pad with a larger pattern compared with a wiring pattern inside a wiring structure. Here, the electrode pad is for electrically connecting an element region of the LSI and the outside, for characteristic evaluations in the development such as a circuit test after an LSI semiconductor structure is formed and a TEG (Test Element Group). Accordingly, it is a whole wiring with a size of approximately 40 μm to 100 μm.
A semiconductor is generally formed on a circular substrate called a wafer, and after completion of a manufacturing process, cut out as chips, and then processed into plastic packages or ceramic packages which can prevent various disturbances from affecting chips. The package has an electrode of an appropriate size for an external circuit, and when wire bonding or bump forming is carried out to electrically connect the electrode pad and an electrode of the package side, a mechanical force is applied to the inside of the pad region, and thereafter a tensile test and the like are carried out to check whether a good connection is performed.
However, when pressure bonding by pushing and the tensile test as described above are carried out, a stress is generated inside the pad region. Since a Young's modulus of a low dielectric constant material is generally low, a low dielectric layer composed of the low dielectric constant material is easily deformed when an external force is applied to the electrode pad, and the applied force is after all supported by a wiring material part of a connection hole formed with a trench pattern or a hole pattern.
As described above, if the interlayer insulating film with the smaller Young's modulus compared with the wiring material is used, the internal stress caused by pressure bonding by pushing at the time of wire bonding to the electrode pad, bump forming and the like as well as by the tensile test and the like, concentrates on the wiring material part. When the stress concentrates on the wiring material part and reaches a yield stress, a function of a wiring in the pad region is disturbed.
The present invention is made in view of the above-described problems, and its object is to provide a semiconductor device in which, when an internal stress occurs in a pad region, the stress is prevented from disproportionately concentrating on a connection hole and deterioration of a function of a wiring caused thereby can be avoided, and a method of manufacturing the same.